1. Field of the Invention
The present invention relates to methods of forming extended arrays of silicon wafer subunits, and more particularly to methods of forming pagewidth arrays by butting multiple print-head subunits into an extended array.
2. Description of Relate
Two preferred methods of forming the butt edges on a subunit are sawing through a silicon wafer or anisotropically etching through a wafer to form subunits having butt edges. Since the step of separating a wafer into subunits by sawing or etching is performed as a batch, well prior to the step of aligning the subunits into arrays, the latter step usually involves selecting subunits from a bin which contains subunits having a variety of thicknesses. For vertical butt edges, B.sub.1, B.sub.2 (FIG. 1A), each subunit S.sub.1 may have a thickness different from the adjacent subunit S.sub.2, thus creating a height difference .DELTA. h between adjacent subunits which forms a step between the integrated circuit IC1 on the circuit surface CS1 of one subunit and the integrated circuit IC2 on the circuit surface CS2 of the adjacent subunit S.sub.2. A benefit of etching is that it does not cause cracking of the silicon wafer passivation layer associated with sawing. Etching, however, forms wafer subunits having diagonal butt edges because the etching occurs along (111) planes of the silicon wafer. When the subunits are formed via etching with diagonal butt edges, B.sub.1, B.sub.2 (FIG. 1B), height h between adjacent silicon subunits S.sub.1, S.sub.2 results in a lateral shift equal to 0.7 .DELTA.h of the circuit surfaces CS1, CS2 of these subunits. These displacements are often unacceptable.
In order to overcome the problem of lateral shifting caused by height differences .DELTA. h between adjacent chips, it has been suggested that adjacent subunit chips can be butted in a flipped orientation (with the integrated circuit facing downwardly). This solves the problem of height differences but requires the delicate circuitry to contact and be moved along a support substrate during the butting procedure. Damage to the integrated circuits, especially the passivation layer, is a possibility. For example, see U.S. Pat. No. 4,690,391 to Stoffel for its disclosure of flipped-chip butting for alignment purposes.
U.S. Pat. No. 4,466,181 to Takashima discloses a method of manufacturing a semiconductive device by positioning plural semiconductive chips on a film so that one of the surfaces of the chips forms a flat plane and connecting the semiconductive chips to one another by applying an insulative material between the chips. The chips are not butted against one another and consequently the problems associated with lateral displacement are not addressed by Takashima. Although the insulative material can be polyimide it is only applied between the chips and not onto the integrated circuit surface of the chip. The conjoined chips of Takashima are not bonded to a substrate and do not form a pagewidth array.
U.S. Pat. No. 4,723,197 to Takiar et al discloses a semiconductor device including a substrate having a surface upon which is located at least one metallization pad, a polyimide layer over the surface, a puncture resistant layer over the polyimide layer and a metal interconnection which penetrates the polyimide layer and the puncture resistant layer to connect with the metallization pad. Although the polyimide layer is used to protect the circuit elements, the present invention is not taught or suggested. The polyimide layer is not applied with a substantially uniform thickness to the circuit surface.
U.S. Pat. No. 4,622,574 to Garcia discloses a semiconductor chip having an upper circuit surface and a peripheral ledge which is recessed below the circuit surface for containing at least one bond pad, and a method of making same. Garcia also discloses a method of fabricating a semiconductor chip from a silicon wafer by forming a groove in the wafer and cutting the wafer within the groove. The present invention is not taught or suggested by Garcia.